Principle of the JFET

In a JFET, the current varies because of the effects of an electric field within the device. Charge carriers (electrons or holes) flow from the source (S) electrode to the drain (D) electrode. This results in a drain current, ID, that is normally the same as the source current, IS. The rate of flow of charge carriers—that is, the current—depends on the voltage at a control electrode called the gate (G). Fluctuations in gate voltage, EG, cause changes in the current through the channel, which is the path between the source and the drain. The current through the channel is normally equal to ID. Small fluctuations in EG can cause large variations in ID. This fluctuating drain current can produce significant fluctuations in the voltage across an output resistance.

N-Channel versus P-Channel

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At A, pictorial diagram of an N-channel JFET. At B, the schematic symbol. Electrodes are S = source, G = gate, and D = drain.
A simplified drawing of an N-channel JFET, and its schematic symbol, are shown in above figure. The N-type material forms the channel, or the path for charge carriers. The majority carriers are electrons. The drain is placed at a positive dc voltage with respect to the source.
 
In an N-channel device, the gate consists of P-type material. Another section of P-type material, called the substrate, forms a boundary on the side of the channel opposite the gate. The voltage on the gate produces an electric field that interferes with the flow of charge carriers through the channel. The more negative EG becomes, the more the electric field chokes off the current through the channel, and the smaller ID becomes.
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At A, pictorial diagram of a P-channel JFET. At B, the schematic symbol. Electrodes are S = source, G = gate, and D = drain.
A P-channel JFET (above figure) has a channel of P-type semiconductor. The majority charge carriers are holes. The drain is negative with respect to the source. The more positive EG gets, the more the electric field chokes off the current through the channel, and the smaller ID becomes.
 
You can recognize the N-channel JFET in schematic diagrams by the arrow pointing inward at the gate, and the P-channel JFET by the arrow pointing outward. Also, you can tell which is which (sometimes arrows are not included in schematic diagrams) by the power-supply polarity. A positive drain indicates an N-channel JFET, and a negative drain indicates a P-channel JFET.
 
In electronic circuits, N-channel and P-channel devices can do the same kinds of things. The main difference is the polarity. An N-channel device can almost always be replaced with a P-channel JFET, and the power-supply polarity reversed, and the circuit will still work if the new device has the right specifications. Just as there are different kinds of bipolar transistors, there are various types of JFETs, each suited to a particular application. Some JFETs work well as weak-signal amplifiers and oscillators; others are made for power amplification.
 
Field effect transistors have certain advantages over bipolar transistors. Perhaps the most important is that FETs are available that generate less internal noise than bipolar transistors. This makes them excellent for use as weak-signal amplifiers at very high or ultrahigh frequencies. Field effect transistors have high input impedance, which can also be an advantage in weak-signal amplifiers.

Depletion and Pinchoff

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At A, the depletion region (darkest area) is narrow, the channel (white area) is wide, and many charge carriers (heavy dashed line) flow. At B, the depletion region is wider, the channel is narrower, and fewer charge carriers flow. At C, the depletion region obstructs the channel, and no charge carriers flow.
The JFET works because the voltage at the gate causes an electric field that interferes, more or less, with the flow of charge carriers along the channel. A simplified drawing of the situation for an N-channel device is shown in above figure.
 
As the drain voltage ED increases, so does the drain current ID, up to a certain level-off value. This is true as long as the gate voltage EG is constant, and is not too large negatively. But as EG becomes increasingly negative (above figure A), a depletion region (shown as a solid dark area) begins to form in the channel. Charge carriers cannot flow in this region; they must pass through a narrowed channel. The more negative EG becomes, the wider the depletion region gets, as shown in drawing B. Ultimately, if the gate becomes negative enough, the depletion region completely obstructs the flow of charge carriers. This condition is called pinchoff, and is illustrated at C.

JFET Biasing

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Two methods of biasing an N-channel JFET. At A, fixed gate bias; at B, variable gate bias.
Two biasing methods for N-channel JFET circuits are shown in above figure.Above figure A, the gate is grounded through resistor R2. The source resistor, R1, limits the current through the JFET. The drain current, ID, flows through R3, producing a voltage across this resistor. The ac output signal passes through C2. In above figure B, the gate is connected through potentiometer R2 to a voltage that is negative with respect to ground. Adjusting this potentiometer results in a variable negative EG between R2 and R3. Resistor R1 limits the current through the JFET. The drain current, ID, flows through R4, producing a voltage across it. The ac output signal passes through C2.
 
In both of these circuits, the drain is positive relative to ground. For a P-channel JFET, reverse the polarities in above figure. Typical power-supply voltages in JFET circuits are comparable to those for bipolar transistor circuits. The voltage between the source and drain, abbreviated ED, can range from about 3 V to 150 V dc; most often it is 6 to 12 V dc. The biasing arrangement in above figure A is preferred for weak-signal amplifiers, low-level amplifiers, and oscillators. The scheme at B is more often employed in power amplifiers having substantial input signal amplitudes.