Common source configuration. This diagram shows an N-channel JFET circuit.
There are three different circuit hookups for FETs, just as there are for bipolar transistors. These three arrangements have the source, the gate, or the drain at signal ground. In the common source circuit, the source is placed at signal ground. Signal input is applied to the gate. The general configuration is shown in above figure. An N-channel JFET is used here, but the device could be an N-channel, depletion-mode MOSFET and the circuit diagram would be the same. For an N-channel enhancement-mode device, an extra resistor would be necessary, running from the gate to the positive power supply terminal. For P-channel devices, the supply would provide a negative, rather than a positive, voltage.
Capacitor C1 and resistor R1 place the source at signal ground while elevating the source above ground for dc. The ac signal enters through C2. Resistor R2 adjusts the input impedance and provides bias for the gate. The ac signal passes out of the circuit through C3. Resistor R3 keeps the output signal from being shorted out through the power supply. The circuit of above figure is the basis for low-level RF amplifiers and oscillators.
The common source arrangement provides the greatest gain of the three FET circuit configurations. The output is 180° out of phase with the input.