Common gate configuration. This diagram shows an N-channel JFET circuit.
In the common gate circuit (above figure), the gate is placed at signal ground. The input is applied to the source. The illustration shows an N-channel JFET. For other types of FETs, the same considerations apply as previously described for the common source circuit. Enhancement-mode devices would require a resistor between the gate and the positive supply terminal (or the negative terminal if the MOSFET is P-channel).
The dc bias for the common gate circuit is basically the same as that for the common source arrangement. But the signal follows a different path. The ac input signal enters through C1. Resistor R1 keeps the input from being shorted to ground. Gate bias is provided by R1 and R2. Capacitor
C2 places the gate at signal ground. In some common gate circuits, the gate is directly grounded, and R2 and C2 are not necessary. The output signal leaves the circuit through C3. Resistor R3 keeps the output signal from being shorted through the power supply.
The common gate arrangement produces less gain than its common source counterpart. But a common gate amplifier is not likely to break into unwanted oscillation, making it a good choice for power-amplifier circuits, especially at RF. The output is in phase with the input.