**Relative drain current (I _{D}) as a function of gate voltage (E_{G}) for a hypothetical N-channel JFET.**

The graph of above figure shows ID as a function of EG for a hypothetical N-channel JFET. The drain voltage, ED, is assumed to be constant. When EG is fairly large and negative, the JFET is pinched off, and no current flows through the channel. As EG gets less negative, the channel opens up, and ID begins flowing. As EG gets still less negative, the channel gets wider and ID increases. As EG approaches the point where the S-G junction is at forward breakover, the channel conducts as well as it possibly can. If EG becomes positive enough so the S-G junction conducts, some of the current in the channel leaks out through the gate. This is usually an unwanted phenomenon.

#### The FET Amplifies Voltage

The best amplification for weak signals is obtained when EG is such that the slope of the curve in above figure is the greatest. This is shown roughly by the range marked X. For power amplification, however, results are often best when the JFET is biased at or beyond pinchoff, in the range marked Y.

In either circuit shown in following figure, ID passes through the drain resistor. Small fluctuations in EG cause large changes in ID, and these variations in turn produce wide swings in the dc voltage across R3 (in the circuit at A ) or R 4 (in the circuit at B). The ac part of this voltage goes through capacitor C2, and appears at the output as a signal of much greater ac voltage than that of the input signal at the gate.

**Two methods of biasing an N-channel JFET. At A, fixed gate bias; at B, variable gate bias.**

#### Drain Current versus Drain Voltage

Do you suspect that the current ID, passing through the channel of a JFET, increases in a linear manner with increasing drain voltage ED? This seems reasonable, but it is not what usually happens. Instead, ID rises for awhile as ED increases steadily, and then ID starts to level off. The current ID can be plotted graphically as a function of ED for various values of EG. When this is done, the result is a family of characteristic curves for the JFET. The graph of above figure shows a family of characteristic curves for a hypothetical N-channel device. The graph of ID versus EG, one example of which is shown in topmost figure, is also an important specification that engineers consider when choosing a JFET for a particular application.

#### Transconductance

This is a measure of how well a bipolar transistor amplifies a signal. The JFET equivalent of this is called dynamic mutual conductance or transconductance. Refer again to top figure. Suppose that EG is a certain value, resulting in a certain current ID. If the gate voltage changes by a small amount dEG, then the drain current will change by a certain increment dID. The transconductance is the ratio dID/dEG. Geometrically, this translates to the slope of a line tangent to the curve of above top figure. The value of dID/dEG is not the same at every point along the curve. When the JFET is biased beyond pinchoff, in the region marked Y, the slope of the curve is zero. Then there is no fluctuation in ID when EG changes by small amounts. There can be a change in ID when there is a change in EG only when the channel conducts current. The region where the transconductance, dID/dEG, is the greatest is the region marked X, where the slope of the curve is steepest. This region of the curve represents conditions where the most gain can be obtained from the device.